1. Field of the Invention
The present invention relates to a digital serial interface circuit, more particularly relates to a serial interface circuit connected to a storage apparatus such as an HDD (hard disk drive), DVD (digital versatile disk)-ROM, CD (compact disk)-ROM, and tape streamer.
2. Description of the Related Art
In recent years, as an interface for transfer of multi-media data, the IEEE (The Institute of Electrical and Electronic Engineers) 1394 high performance serial bus for realizing high speed data transfer and real time transfer has become the standard.
In the data transfer by this IEEE 1394 serial interface, the transfer operation carried out in a network is referred to as a xe2x80x9csub-actionxe2x80x9d. Two sub-actions are prescribed.
One is an asynchronous transfer mode for making conventional requests, requesting acknowledgment, and confirming reception, while the other is an isochronous transfer mode in which the data is always sent from a certain node one time in 125 xcexcs.
In this way, the data at an IEEE 1394 serial interface having the two transfer modes is transferred in units of packets. In the IEEE 1394 standard, however, the smallest unit of data which is handled is a quadlet (=4 bytes=32 bits).
In the IEEE 1394 standard, usually the computer data is transferred by using the asynchronous transfer mode as shown in FIGS. 4A and 4B.
The asynchronous transfer mode, as shown in FIG. 4A, includes three transition states, that is, arbitration (arb) for securing the bus, packet transmission for transferring the data, and acknowledgment (ack).
The packet transmission is executed by the format as shown in FIG. 4B.
A first quadlet of the transfer packet is comprised of a destination ID region of 16 bits, a transaction label (t1) region of 6 bits, a retry code (rt) region of 2 bits, a transaction code (tcode) region of 4 bits, and a priority (pri) region of 4 bits.
The destination ID region indicates a bus no. and a node no. of this node, while the priority region indicates a priority level.
A second quadlet and a third quadlet are comprised by a source ID region of 16 bits and a destination offset region of 48 bits.
The source ID region indicates the node ID which sent the packet, while the destination offset region is comprised by a region of continuous highs and lows and indicates an address of an address space of the destination node.
A fourth quadlet is comprised by a data length region of 16 bits and an extended transaction code (extended tcode) region of 16 bits.
The data length region indicates the number of bytes of the received packet, while the extended tcode region is a region indicating an actual lock action carried out by the data of this packet where the tcode indicates a lock transaction.
A header CRC region added to the quadlet before the data field region is an error detection code of the packet header.
Further, the data CRC region added to the quadlet after the data region (data field) is the error detection code of the data field.
As explained above, in the usual transfer of computer data carried out in the asynchronous transfer mode, SBP-2 (Serial Bus Protocol-2) is used as the protocol.
According to this protocol, when data is transferred from a storage device, that is, a target, to a host computer, that is, an initiator, the transfer is carried out by writing the data from the storage device to a memory of the host computer. When data is transferred from the host computer to the target, the transfer is carried out by the storage device reading the data of the memory of the host computer.
However, no processing circuit system has yet been established for controlling a so-called xe2x80x9ctransaction layerxe2x80x9d for converting the large volume of data to be stored in the storage device or read from the storage device into packets of the IEEE 1394 standard for transmission and reception.
An object of the present invention is to provide a serial interface circuit capable of converting a large volume of data into packets based on a predetermined standard for transmission and reception and of performing smooth transmission and reception processing.
To attain the above object, according to a first aspect of the present invention, there is provided a serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising a storage means, a transmission packet generation circuit for generating a request packet containing a size of data to be transferred when transferring the data of the other node to its own node, a comparison means for comparing the size of data requested by the request packet and remaining amount of the storage means, and a data processing circuit which, when the result of the comparison of the comparison means is that the remaining amount of the storage means is larger than the requested size of data, transmits the request packet to the serial interface bus and which, when receiving a response packet with respect to the request packet from the other node, stores at least a data portion of the response packet in the storage means.
According to a second aspect of the present invention, there is provided a serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising a first storage means, a second storage means, a transmission packet generation circuit for generating a request packet containing a size of data to be transferred and storing the same in the first storage means when transferring the data of the other node to its own node, a comparison means for comparing the size of data requested by the request packet and remaining amount of the second storage means, and a data processing circuit which, when the result of the comparison of the comparison means is that the remaining amount of the second storage means is larger than the requested size of data, transmits the request packet to the serial interface bus and which, when receiving a response packet with respect to the request packet from the other node, stores at least a data portion of the response packet in the second storage means.
According to a third aspect of the present invention, there is provided a serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising a storage means, a transmission packet generation circuit for generating a request packet containing a size of data to be transferred when transferring the data of the other node to its own node, a maximum size calculating circuit for obtaining a maximum size of data which can be requested by the request packet, a comparison means for comparing the maximum size of data obtained by the maximum size calculating circuit and remaining amount of the storage means, and a data processing circuit which, when the result of the comparison of the comparison means is that the remaining amount of the storage means is larger than the maximum size of data, transmits the request packet to the serial interface bus and which, when receiving a response packet with respect to the request packet from the other node, stores at least the data portion of the response packet in the storage means.
According to a fourth aspect of the present invention, there is provided a serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising a first storage means, a second storage means, a transmission packet generation circuit for generating a request packet containing a size of data to be transferred and storing the same in the first storage means when transferring the data of the other node to its own node, a maximum size calculating circuit for obtaining a maximum size of data which can be requested by the request packet, a comparison means for comparing the maximum size of data obtained by the maximum size calculating circuit and remaining amount of the second storage means, and a data processing circuit which, when the result of the comparison of the comparison means is that the remaining amount of the second storage means is larger than the maximum size of data, transmits the request packet to the serial interface bus and which, when receiving a response packet with respect to the request packet from the other node, stores at least a data portion of the response packet in the second storage means.
Preferably, in the above aspects, the transmission packet generation circuit, when transferring data of the other node to its own node, generates a plurality of request packets containing the size of data to be transferred and transmits the same to the serial interface bus to enable transfer of the data in packets.
Alternatively, in the above aspects, the transmission packet generation circuit, when transferring data of the other node to its own node, generates a plurality of request packets containing the size of data to be transferred and transmits the same to the serial interface bus to enable transfer of the data in packets.
According to the circuit of the present invention when transferring data from another node to its own node, the request packet containing the size of the data to be transferred is generated by the transmission packet generating circuit and is input to the data processing circuit (or stored in the first storage means).
In the comparison means, the size of the data requested by the request packet and the remaining amount of the storage means (or the second storage means) are compared.
When the result of the comparison is that the remaining amount of the storage (or the second storage means) is larger than the size of the requested data, the request packet is transmitted from the data processing circuit to the serial interface circuit.
When the response packet with respect to the request packet from another node is received, at least the data portion of the response packet is stored in the storage means (or the second storage means).
Further, according to the circuit of the present invention, when transferring data from another node to its own node, a request packet containing the size of the data to be transferred to enable transfer of the data in packets is generated and is input to the data processing circuit (or stored in the first storage means).
In the maximum size calculating circuit, the maximum size of the data requested by the request packet is obtained and is input to the comparison means.
In the comparison means, the maximum size of the data and the remaining amount of the storage means (or the second storage means) are compared.
When the result of the comparison is that the remaining amount of the storage means (or the second storage means) is larger than the maximum size of data, the request packet is transmitted from the data processing circuit to the serial interface circuit.
When a request packet with respect to the response packet from another node is received, at least the data portion of the response packet is stored in the storage means (or the second storage means).